Semiconductor integrated circuit

ABSTRACT

Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≥2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≥M≥2) times the basic cell length which is appropriate to the single complementary transistor pair.

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 8,357,955. The reissue applications are applicationSer. No. 15/882,412 (the present application), application Ser. No.15/078,990 and application Ser. No. 14/600,627, all of which arereissues of U.S. Pat. No. 8,357,955.

The present application is a continuation reissue application of parentreissue application Ser. No. 15/078,990, filed Mar. 23, 2016, now U.S.Pat. No. RE47,095, which is a continuation reissue application of parentreissue application Ser. No. 14/600,627, filed Jan. 20, 2015, now U.S.Pat. No.: RE45,988, issued on Apr. 26, 2016, which is a reissueapplication of application Ser. No. 12/805,158, filed Jul. 15, 2010, nowU.S. Pat. No. 8,357,955, issued Jan. 22, 2013. The present inventioncontains subject matter related Japanese Patent Application JP2009-198547 filed in the Japan Patent Office on Aug. 28, 2009, theentire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuithaving a desired circuit formed by combining and laying out a pluralityof standard cells each having transistors and gate electrodes andconnecting the cells together.

2. Description of the Related Art

In a common standard cell, at least one of the sizes thereof in thedirections orthogonal to each other (so-called vertical and horizontaldirections) is standardized to a few types or, for example, to threetypes. The so-called vertical size is referred to as the height of thestandard cell. This height is standardized to three types or so. Here,in order to avoid confusion between this cell size (height) and itsstructural height perpendicular to the semiconductor substrate, the cellsize will not be called the “height.” Instead, this size will bereferred to as the “standard cell length” for the sake of convenience.

Even when a few standard lengths of the standard cell may be used in anLSI (Large Scale Integration) as a whole, the same standard length isused when viewed locally as in the same circuit block to ensureefficient layout of cells.

Therefore, various types of standard cells with the same standard celllength are made available and registered in a library. In general,standard cell patterns such as internal wiring patterns are limited inlayout space along the standard cell length.

In contrast, the standard cell size in the direction orthogonal to thecommon cell length (so-called horizontal direction) is available in avariety of lengths according to the scale of the gate circuit. The cellsize in the direction orthogonal to the common cell length will behereinafter referred to as the “arbitrary cell length” for the sake ofconvenience.

The inverter is normally the most basic building block of logic circuitsachieved by the standard cell system. The inverter is formed byconnecting NMOS and PMOS transistors in series between VDD and VSS linesso that the gates are shared. In the most basic standard cell used forlogic circuits, the distance between the center of the VDD line and thatof the VSS line is the standard cell length, and the direction along theVDD and VSS lines is the arbitrary cell length direction when the VDDand VSS lines are arranged alternately and parallel to each other. Thismost basic standard cell is designed by increasing or reducing the sizeof the arbitrary cell length as appropriate according to the scale ofthe standard cell circuit. Such a basic standard cell has a standardcell length of a CMOS pair that is appropriate to the sum of the lengthsof NMOS and PMOS gates. Such a standard cell has a height appropriate tothat of a single CMOS pair. Therefore, this cell will be hereinafterreferred to as a “single height cell.”

The layout of standard cells each having a standard cell length of aCMOS pair is described, for example, in Japanese Patent Laid-Open No.Hei 10-173055.

SUMMARY OF THE INVENTION

There would be no problems if the circuit to be achieved with a standardcell was a basic logic gate circuit such as an inverter or a NANDcircuit. However, there are cases in which the single heightconfiguration is not suitable depending on the circuit scale.

We assume, for example, that there is a standard cell configured in sucha manner that the gates of a number of CMOS pairs must be driven inphase.

In this standard cell, the PMOS and NMOS transistor gates in each CMOSpair are connected by a gate line made, for example, of polysilicon.However, several gate lines must be further shorted together. Therefore,the gate lines are connected together by upper layer wirings (normally,metal wirings in the first layer). However, a number of other internalwirings are also required in the standard cell to connect transistorgates to the sources or drains of other transistors. As a result, it maybe impossible to secure a space to connect the gates together with theupper layer wirings.

Even if a space is secured, it may be necessary to design wirings thatare bent in a complex manner, thus resulting in reduced workability fordesign and mask preparation and leading to higher cost.

If a space cannot be secured, there is no alternative but to increasethe standard cell length in the standard cell specification to providemore leeway or use the wirings in a higher layer.

However, increasing the standard cell length leads to waste in areasother than the CMOS pairs of the cell and small-scale basic circuitrysuch as inverters. Moreover, using the wirings in a higher layer (e.g.,wirings in the second metal wiring layer) clutters the space where otherwirings are supposed to be formed in the second metal wiring layer.

It is desirable to provide a semiconductor integrated circuit having acell layout unlikely to produce wasted space and advantageous in termsof cost when the semiconductor integrated circuit contains standardcells for achieving a circuit adapted to drive a plurality ofcomplementary transistor pairs (e.g., CMOS pairs) in phase.

In a semiconductor integrated circuit according to an embodiment of thepresent invention, a desired circuit is formed by combining and layingout a plurality of standard cells and connecting the cells together. Thecell length, i.e., as the gap between a pair of opposed sides, of thestandard cells is standardized. These standard cells include acomplementary in-phase driven standard cell. Each of the complementaryin-phase driven standard cell includes a plurality of complementarytransistor pairs that are complementary in conductivity type to eachother and have their gate electrodes connected together. N (≥2) pairs ofall the complementary transistor pairs are driven in phase. Further, thesize of the standardized cell length of a complementary in-phase drivenstandard cell is defined as an M-fold cell length which is M (N≥M≥2)times the basic cell length which is appropriate to the singlecomplementary transistor pair. In a complementary in-phase drivenstandard cell, the common gate electrodes of at least M pairs of the Ncomplementary transistor pairs to be driven in phase are arrangedlinearly in the direction of the M-fold cell length.

In the embodiment of the present invention, single height cells orstandard cells having the basic cell length and multi-height cells orthe complementary in-phase driven standard cells having the M-fold celllength, are preferably arranged adjacent to each other to form thedesired circuit. Further, when arranged adjacent to the single heightcells, the multi-height cells preferably have a power line arrangementstructure that allows for power lines to be shared.

In the above configuration of the semiconductor integrated circuitaccording to the embodiment of the present invention, if electricalshorting is required for in-phase driving, the gate electrodes of aplurality of complementary transistor pairs to be driven in phase areformed integrally with a common gate line itself. This provides areduced number of internal wirings required to short the gate lines,thus eliminating wasted space. Further, this eliminates the need to forminternal wirings in complex shapes.

The above preferable configuration does not impede the advantages of thestandard cell layout system because the multi-height cells preferablyhave a power line sharing structure with the adjacent single heightcells. At this time, the single height cells need only have a requiredminimum basic cell length suitable for a small-scale circuit. Thestandard cell length of the multi-height cell is a plurality of timesthe basic cell length thereof. This makes it possible to secure a powerline sharing structure with other surrounding cells even if the standardcell length of the multi-height cell is increased. Further, in thiscase, the single height cell has a required minimum basic cell lengthsuitable for a small-scale circuit, thus eliminating wasted space.

The present invention provides a semiconductor integrated circuit havinga cell layout unlikely to produce wasted space and advantageous in termsof cost when the semiconductor integrated circuit contains standardcells for achieving a circuit adapted to drive a plurality ofcomplementary transistor pairs (e.g., CMOS pairs) in phase.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram schematically illustrating a plan view of anintegrated circuit according to first to third embodiments with a focuson the cell layout;

FIGS. 2A to 2C are layout diagrams for describing the inconveniences ofa single height layout technique;

FIG. 3 is an equivalent circuit diagram of a first application examplein the first embodiment;

FIG. 4 is a first layout diagram of a first application example in thefirst embodiment;

FIG. 5 is a layout diagram of comparison example 1 in the firstembodiment;

FIGS. 6A and 6B are equivalent circuit diagrams of a second applicationexample in the first embodiment;

FIG. 7 is a first layout diagram of a second application example in thefirst embodiment;

FIG. 8 is a second layout diagram of the second application example inthe first embodiment;

FIG. 9 is a layout diagram of comparative example 2 in the firstembodiment;

FIG. 10 is an equivalent circuit diagram of a third application examplein the first embodiment;

FIG. 11 is a layout diagram of the third application example in thefirst embodiment;

FIGS. 12A and 12B are equivalent circuit diagrams of a fourthapplication example in the first embodiment;

FIG. 13 is a layout diagram of the fourth application example in thefirst embodiment;

FIG. 14 is a layout diagram in a second embodiment;

FIG. 15 is a layout diagram in a third embodiment;

FIG. 16 is a first layout diagram of a modification example; and

FIG. 17 is a second layout diagram of the modification example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description will be given below of embodiments of the presentinvention with reference to the accompanying drawings by taking, as mainexamples, double height and triple height circuit cells.

1. First embodiment: Embodiment in which the double height cell to whichthe present invention is applied is shown by four application examples(circuit examples). In the first and second application examples, theeffect obtained by the application of the present invention will bedescribed by using comparative examples 1 and 2.2. Second embodiment: Embodiment of a triple height cell to which thepresent invention is applied.3. Third embodiment: Embodiment of an L-shaped cell (double height cellhaving the same functionality as a triple height cell) to which thepresent invention is applied.4. Modification examples: Two modification examples relating to asubstrate contact will be described.

1. First Embodiment 1. Overall Layout

FIG. 1 is a diagram schematically illustrating a plan view of anintegrated circuit according to embodiments with a focus on the celllayout.

In FIG. 1, each of rectangular areas is called a cell. The cells denotedby reference numeral SC are standard cells. The standard cell SC is apredesigned and standardized functional circuit cell registered in alibrary such as an inverter or a NAND gate. Although being a collectionof data, the standard cell SC may refer to part of a device manufacturedbased on the data. Although a detailed description will be given later,standard cells registered in a library are combined and laid out in thedesign phase of a semiconductor integrated circuit. As a result of thelayout, source voltage lines and reference voltage lines (e.g., GNDlines) are roughly connected together on data. Connecting signal andother lines after the layout provides the desired circuit. The layout ofcells and disposition of wirings up to this point is conducted on thedata level using a design support apparatus.

Although being a schematic plan view of the semiconductor integratedcircuit with a focus on the cell layout, FIG. 1 can also serve as adata-level cell layout diagram.

In a semiconductor integrated circuit 1 shown in FIG. 1, the standardcells SC of a variety of sizes are combined and laid out, thus achievinga desired circuit. Here, the desired circuit can be achieved at willdepending on what the functional circuits of the standard cells SC areand how the cells are combined so long as the desired circuit is a logiccircuit. FIG. 1 is a generalized diagram, and it is arbitrary what thedesired circuit is.

The standard cell design system is used in the design process of ASIC(Application Specific Integrated Circuit) and ASSP (Application SpecificStandard Product). ASIC is an IC developed and manufactured to meet aspecific application requirement of each customer. ASSP is an ICdesigned and developed as a general-purpose part for a plurality ofcustomers.

A description will be given below of the size of the standard cell SC.

In the standard cell SC, the cell length in the direction along one oftwo sides that are orthogonal to each other is commonly standardized.This cell length direction will be hereinafter referred to as the“standard cell length direction.” There may not be only one, but a fewsizes or, for example, three sizes, in the standard cell lengthdirection (standard cell lengths) in an entire IC. It should be noted,however, that there has been, up until today, one unified standard celllength, when viewed locally, as in a single circuit block or a circuitadapted to achieve a desired function. One of the major characteristicsof the embodiments of the present invention is that there are aplurality of standard cell lengths in a local circuit such as a singlecircuit block or a circuit adapted to achieve a desired function.

In relation to this characteristic, common single height standard cellsSHSC and multi-height standard cells MHSC, both serving as the standardcells SC, are mixed in the example shown in FIG. 1. Here, two types ofmulti-height standard cells MHSC are shown, a double height standardcell WHSC having a standard cell length twice that of a single heightstandard cell SHSC and a triple height standard cell THSC having astandard cell length that is three times that of a single heightstandard cell SHSC.

The cell size can be determined at will in the direction orthogonal tothe standard cell length direction. Although the cell size may bedetermined at will, it is common that there are fixed discrete sizesthat can be used (specified by the grid number) for reasons of designefficiency or to meet the demand for consistency. The directionorthogonal to the standard cell length direction will be hereinafterreferred to as the “arbitrary cell length direction.”

In a circuit block as shown in FIG. 1, the VDD and VSS lines extend inthe arbitrary cell length direction and are arranged alternately in thestandard cell length direction. The gap between the VDD and VSS lines isappropriate to the height of the single height standard cell SHSC.

Further, the double height standard cell WHSC includes a type denoted byreference numeral WHSC1. The double height standard cell WHSC1 has thetwo VSS lines that are disposed, one along each of the two short sides,in the standard cell length direction, with the VDD line passing throughthe same cell WHSC1 at the center between the two VSS lines. Further,the double height standard cell WHSC includes a type denoted byreference numeral WHSC2. In contrast to the double height standard cellWHSC1, the double height standard cell WHSC2 has the two VDD lines thatare disposed, one along each of the two short sides, with the VSS linepassing through the same cell WHSC2 at the center between the two VDDlines. Although only one of these two types may be used, the two typesare mixed here from the viewpoint of layout efficiency.

[Single Height Layout]

Next, the reason will be clarified why the single height standard cellsSHSC and multi-height standard cells MHSC are mixed in the same circuitblock by stating the disadvantages of the major techniques adapted todesign a semiconductor integrated circuit with only single height cells.

FIGS. 2A to 2C illustrate three types of single height standard cellsdesigned by a single height layout technique to form a CMOS logiccircuit.

Each of these single height standard cells SHSC_1, SHSC_2 and SHSC_3 hastwo doped regions, namely, a P-type doped region 13P and an N-type dopedregion 13N, arranged parallel to each other between the VDD and VSSlines. The P-type doped region 13P serves as the sources or drains ofPMOS transistors. The N-type doped region 13N serves as the sources ordrains of NMOS transistors. The reason for this is that the inverter isthe basic building block of CMOS logic circuits. Polysilicon gateelectrodes 20A and 20B forming an inverter input are arranged linearlyso as to be orthogonal to a rectangular region including a P-type dopedregion 13P (hereinafter denoted by the same reference numeral as theP-type doped region 13P and referred to as the “PMOS active region13P”). The polysilicon gate electrodes 20A and 20B are also arrangedlinearly so as to be orthogonal to a rectangular region including anN-type doped region 13N (hereinafter denoted by the same referencenumeral as the N-type doped region 13N and referred to as the “NMOSactive region 13N”) (FIGS. 2A and 2C). Therefore, the single heightstandard cells have a height (standard cell length) appropriate to thatof a complementary transistor pair (NMOS and PMOS pair).

In such a standard cell configuration, vertically long common gateelectrodes of the complementary transistor pair (hereinafter the CMOSgate lines) are arranged side by side. This leads to an increased numberof internal wirings adapted to connect CMOS gate lines or a CMOS gateline and other node (e.g., transistor source and drain). Moreover,because such a number of internal wirings must be provided in a limitedspace, the wiring pattern is inevitably complex. This leads to manyvertices and bends in the metal and polysilicon layouts, thus resultingin a complex shape.

In leading-edge processes, the more complex the pattern shape is, themore design rule restrictions are imposed. Further, a complex patternshape leads to a long time required to perform optical proximitycorrection (OPC) in the mask preparation or is disadvantageous from theviewpoint of design for manufacturing (DFM). Here, the term “DFM (designfor manufacturing)” refers to a technique adapted to resolve the LSImanufacturing problems at the design stage. In the cell layout, a simpleshape provides a device less susceptible to variations at the time ofmanufacture. Therefore, this aspect is important.

Further, difficulty in performing OPC, for example, may lead to areduced yield of physical device.

The viewpoints described above constitute the first disadvantage ofdesigning a logic circuit with only the single height standard cellsSHSC.

A high likelihood of producing wasted space is the second disadvantage.

Standard cells used, for example, for a clock tree may be laid out witha changed size ratio between the PMOS and NMOS to ensure that the clockdelay is the same. For example, a standard cell (SHSC_2: FIG. 2B) may beused that has a larger-than-normal PMOS (SHSC_1: FIG. 2A).Alternatively, a standard cell (SHSC_3: FIG. 2C) may be used that has asmaller-than-normal NMOS.

In this case, enlarging the PMOS active region 13P horizontally leads toa vacancy in the NMOS transistor forming region as shown in FIG. 2B.Conversely, reducing the NMOS active region 13N vertically does notincrease the area of the standard cell SC itself but leads to a reducedarea usage efficiency. These constitute wasted spaces in exchange fornecessary functions, which is one of the reasons why high densitypackaging cannot be achieved.

The embodiments of the present invention propose a complementarytransistor pair (e.g., CMOS pair) standard cell configuration thatresolves the above two disadvantages. The present invention is appliedto a complementary in-phase driven standard cell of all the types ofcomplementary transistor pair standard cells.

Three layout configuration examples of the complementary in-phase drivendouble height standard cells WHSC to which the present invention isapplied will be shown below together with circuit examples.

First Application Example

FIG. 3 is an equivalent circuit diagram of a half adder cell as acircuit example of the standard cell SC to which the present inventionis applied. The half adder shown in FIG. 3 is broadly divided into acarry-out section (CO section) and a single-bit addition section (Sumsection). The half adder is a circuit designed to receive first andsecond input bits (A1 and A2) and output a half addition bit (S) and acarry-out bit (hereinafter the CO bit). The half addition bit representsthe result of half addition in the first digit. The CO bit represents acarry.

It should be noted that the gates of the CMOS pairs that are supplied,for example, with the same input in FIG. 3 are indicated bybi-directional arrows.

The carry-out (CO) section includes a NAND circuit and an inverter. TheNAND circuit includes two PMOS transistors P1 and P2 and two NMOStransistors N1 and N2. The inverter includes a PMOS transistor P3 and anNMOS transistor N3. The NAND circuit and inverter are connected by awiring denoted by reference numeral 31 (internal wiring 31) where aninverted carry-out bit (NCO) appears. The P1-N1 CMOS pair is suppliedwith the first input bit A1. The P2-N2 CMOS pair is supplied with thesecond input bit A2.

The single-bit addition (Sum) section includes four PMOS transistors P4to P7 and four NMOS transistors N4 to N7 and has the inverted carry-outbit (NCO) and the first and second input bits (A1 and A2) as its inputs.Although performing a single bit addition, the same section produces asingle bit output. Therefore, the same section performs a half additionoperation adapted to produce a “0” output with the help of the invertedcarry-out bit (NCO) that is “0 (e.g., low level)” when both the firstand second input bits A1 and A2 are “1 (e.g., high level).”

In such a configuration, when the two input bits (A1 and A2) are bothlow, the PMOS transistors P1 and P2 are ON. Therefore, the NCO is high,and the CO is low. As a result, no carry is generated. On the otherhand, both the PMOS transistors P5 and P6 are ON. This pulls an invertedhalf addition bit (NS) up to high level. The NS is the potential of aninternal connection line 33 forming the input node of the inverter atthe final stage. As a result, an internal connection line 34 outputs alow level as the half addition bit (S).

When the two input bits (A1 and A2) are high and low, respectively, thePMOS transistor P1 is OFF but the PMOS transistor P2 is ON. Similarly,therefore, the NCO is high, and the CO is low. As a result, no carry isgenerated. On the other hand, both the NMOS transistors N4 and N5 areON. This pulls the inverted half addition bit (NS) down to low level.Therefore, a high level is output as the half addition bit (S).

When the two input bits (A1 and A2) are low and high, respectively, thePMOS transistor P2 is OFF but the PMOS transistor P1 is ON. Similarly,therefore, the NCO is high, and the CO is low. As a result, no carry isgenerated. On the other hand, both the NMOS transistors N4 and N5 areON. This pulls the inverted half addition bit (NS) down to low level.Therefore, a high level is output as the half addition bit (S).

When the two input bits (A1 and A2) are both high, the NMOS transistorsN1 and N2 are ON, which stands in contrast to the above three cases.Therefore, the NCO is low, and the CO is high. As a result, a carry isgenerated. On the other hand, because the NCO is low, the PMOStransistor P4 is ON although the PMOS transistors P5 and P6, provided inparallel with the PMOS transistor P4, are OFF. This pulls the invertedhalf addition bit (NS) up to high level. Therefore, a low level isoutput as the half addition bit (S).

FIG. 4 is a layout diagram of the circuit shown in FIG. 3 designed byapplying an embodiment of the present invention.

The standard cell illustrated in FIG. 4 is an example of the doubleheight standard cell WHSC1 (FIG. 1) having the VDD line disposed at thecenter.

In this double height standard cell WHSC1, a VDD line 30D extends in thearbitrary cell length direction (horizontal direction) at the center ofthe standard cell length direction (vertical direction). Further, twoVSS lines, i.e., VSS lines 30S1 and 30S2, are disposed. The VSS line30S1 is arranged along the center of the width of one of the short sidesof the horizontal outer frame of the cell. The VSS line 30S2 is arrangedalong the center of the width of the other of the short sides thereof.The VSS lines 30S1 and 30S2 are arranged parallel to each other, andalso parallel to the VDD line 30D. The VDD line 30D and VSS lines 30S1and 30S2 are formed by patterning the first wiring layer (1M).

The circuit (CO section) adapted to generate the carry-out bit (CO bit)is provided on the lower half of the cell in such a manner as to havethe VSS line 30S1 and share the VDD line 30D. On the other hand, thecircuit (Sum section) adapted to generate the half addition bit (S) isprovided on the upper half of the cell in such a manner as to have theVSS line 30S2 and share the VDD line 30D.

Two active regions of the same conductivity type, i.e., PMOS activeregions 11P and 12P, are arranged line-symmetrically with respect to thecenter line of the power line (VDD line 30D) passing through the cell.Further, an NMOS active region 11N is arranged between the PMOS activeregion 11P and VSS line 30S1, and an NMOS active region 12N between thePMOS active region 12P and VSS line 30S2.

Surrounded by an element isolation insulating layer 10, these fouractive regions are isolated from one another and arranged to behorizontally long in shape and parallel to the power line.

It should be noted that the CO section has six transistors whereas theSum section has eight. Therefore, the PMOS and NMOS active regions 12Pand 12N are longer in shape than the NMOS and PMOS active regions 11Nand 11P.

Three common gate electrodes 21 to 23 are arranged linearly in such amanner as to penetrate the four active regions vertically (in thestandard cell length direction).

The common gate electrode 21 serves as a common gate of the transistors(P1, N1, P5 and N5) adapted to receive the first input bit A1 shown inFIG. 3. The positions of the above transistors are shown in FIG. 4 bythe same reference numerals.

The common gate electrode 22 serves as a common gate of the transistors(P2, N2, P6 and N6) adapted to receive the second input bit A2 shown inFIG. 3. Further, the common gate electrode 23 serves as a common gate ofthe transistors (P3, N3, P4 and N4) adapted to receive the invertedcarry-out bit shown in FIG. 3. The positions of the above transistorsare also shown in FIG. 4 by the same reference numerals.

On the other hand, a common gate electrode 24 for the remaining twotransistors (P7 and N7) is shorter than the other three and penetratesthe PMOS and NMOS active regions 12P and 12N because the two transistorsmust receive the inverted half addition bit (NS) in the Sum section.

Internal wirings 31 to 35 shown in FIG. 3 are provided as the wirings ofthe first wiring layer (1M) and shaped as shown in FIG. 4 to connect thesources, drains and gates of different transistors. The specificconnection relationship is obvious with reference to FIG. 3, andtherefore is omitted.

[Characteristics of the Layout to Which the Present Invention isApplied]

A first characteristic of the layout is that the connection rule withthe single layout power line arrangement is maintained. That is, therelationship between the VSS line 30S1 and VDD line 30D and that betweenthe VSS line 30S2 and VDD line 30D are appropriate to the standard celllength of the single height standard cell SHSC (FIG. 1). Theserelationships allow for power lines to be shared between a single heightcell and double height cell when they are arranged adjacent to eachother. For this reason, the double height standard cell WHSC1 has astandard cell length which is a plurality of or M (≥2, M=2 in this case)times the basic cell length which is the standard cell length of asingle height cell.

A second characteristic of the layout is that the gate electrodes of theplurality of or M (M=2 in this case) complementary transistor pairs tobe driven in phase are arranged linearly as common gate electrodes.

This commonization of gate electrodes contributes to a reduced number ofinternal wirings, thus providing leeway in the layout of other internalwirings. When there is leeway in the layout of internal wirings, wiringsmay be laid out without forming a complex shape, possibly contributingto improved yield and ease of manufacturing. Further, there is no needto connect the gates together using the upper layer wirings, thusproviding leeway in the layout of the upper layer wirings. In the caseof this circuit example in particular, there is no need to connect thegates together in the higher second wiring layer, as in the comparativeexamples which will be described layer, thus ensuring effective use ofmulti-wiring resources and providing reduced cost.

A third characteristic of the layout is that active regions of the sameconductivity type (11N and 12N) are arranged line-symmetrically withrespect to (M−1) power lines passing midway therebetween, or the one VDDline 30D because M=2.

A fourth characteristic of the layout is that all the gate electrodesoverlapping the portion of the element isolation insulating layer 10located within the width of separation between the two active regionsare the common gate electrodes 21 to 23 of the complementary transistorpairs to be drive in phase. In contrast, the common gate electrode 24 isnot a common electrode of a plurality of complementary transistor pairs,but is instead a common electrode of NMOS and PMOS transistors in asingle complementary transistor pair. Such an electrode does not overlapany portion of the element isolation insulating layer 10 located withinthe width of separation between the two active regions (instead overlapsthe portion of the same layer 10 located outside the width ofseparation).

The fourth characteristic is obvious when we consider the case in whichthis characteristic is not present. That is, we assume that two gateelectrodes, one extending from up to down and another extending fromdown to up into the width of separation between the two active regions,are separated within the same width. In this case, a space forseparating the electrodes is required in addition to the alignmenttolerance required to reliably align the gate electrodes with the activeregions in consideration of the misalignment of the photomask. As aresult, there are limits to reducing the space between the activeregions.

In the case of the layout shown in FIG. 4 to which the present inventionis applied, on the other hand, the gate electrodes are not separated.Therefore, there is no need to consider the tolerance in this portion,nor there is any need to provide a separation space. All what isrequired is a separation width for element separation. However, so longas this width is secured, it is possible to bring the two active regionsclose to each other to the extent possible, thus providing leeway in thestandard cell length direction. Because the standard cell length isdetermined to be M times the basic cell length which is the standardcell length of a single height cell, the standard cell length can bechanged only by reviewing the basic cell length. This leeway provides alarger channel width (commonly also called the gate length) in thedetermined standard cell length direction, thus contributing to a largertransistor size or providing leeway in the layout of other internalwirings. When there is leeway in the arrangement of internal wirings,wirings may be laid out without forming a complex shape, contributing toimproved yield and ease of manufacturing.

The above characteristics are also available when triple or higherstandard cells which will be described later are used.

A description will be given next of comparative examples to which thepresent invention is not applied to further clarify the effects of theabove characteristics.

Comparative Example 1

FIG. 5 is a layout diagram of comparison example 1 in which the samecircuit (FIG. 3) as shown in FIG. 4 is achieved with horizontally longsingle height cells.

The circuits shown in FIGS. 4 and 5 are basically extremely similarexcept for the communization of gate electrodes. Like components aredenoted by like reference numerals, and the description thereof isomitted.

In FIG. 5, the CO and Sum sections are arranged parallel to each otherbetween the VDD line 30D and a VSS line 30S so that the CO and Sumsections can be supplied with power from these lines.

Further, while the single common gate electrode 21 is linearly arrangedin FIG. 4, two common gate electrodes 21A and 21B, each for a CMOS pair,are arranged one on the left and the other on the right in FIG. 5.Similarly, while the single common gate electrode 22 is provided in FIG.4, two common gate electrodes 22A and 22B are arranged one on the leftand the other on the right in FIG. 5. Still similarly, while the singlecommon gate electrode 23 is provided in FIG. 4, two common gateelectrodes 23A and 23B are arranged one on the left and the other on theright in FIG. 5.

Because the two common gate lines are arranged separately, the pairs ofgate electrodes shown by bi-directional arrows in FIG. 5 must beelectrically shorted together.

A first approach to making these connections would be to achievehorizontal connections using the common gate electrodes themselves (gatepolysilicon layer).

In order to short the common gate electrodes 21A and 21B together, it isnecessary, for example, to expand the space between the PMOS activeregion 11P or 12P and VDD line 30D in the standard cell lengthdirection. Further, in order to short the common gate electrodes 22A and22B together, it is necessary, for example, to expand the space betweenthe NMOS active region 11N or 12N and VSS line 30S in the standard celllength direction. Even in this case, the common gate electrodes 23A and23B cannot be shorted together. As a result, it is inevitable that thisremaining pair of common gate electrodes should be shorted togetherusing the first wiring layer (1M).

With the first approach, the cell length must be expanded in thestandard cell length direction so as to secure a space for arranging twocommon gate electrodes. However, this gives rise to significant wastedspace in the standard cell array as a whole, which makes this approachunacceptable.

For this reason, a second approach would be to use the second wiringlayer (2M).

If the branches for the active region contacts of the power lines (30Dand 30S) and internal wirings (31 to 33) are moved backward in FIG. 5,it seems possible to secure a space for arranging the first wiring layer(1M) adapted to short out at least one common gate line. However, it isimpossible in terms of space to connect all three. Therefore, at leastone of them must use the higher second wiring layer (2M).

On the other hand, the connections between the first and second inputbits A1 and A2 and half addition bit (S) and the unshown adjacent cellare not shown in FIG. 5. The second wiring layer (2M) may be used tomake connections with the adjacent cell, which is, however, notnecessary in the pattern shown in FIG. 5. The input and output lines ofthese three bits can be achieved by changing the pattern of the firstwiring layer (1M).

Even in such a case, the layout shown in FIG. 5 which requires the useof the second wiring layer (2M) merely for connecting the common gateelectrodes is disadvantageous in that it may result in significantlyincreased cost due to wasteful use of wiring resources.

As described above, both the first and second approaches aredisadvantageous in that they are highly likely to result insignificantly increased cost. The layout shown in FIG. 4 is superior tothe comparative example shown in FIG. 5 in that it will not incur such adisadvantage.

It should be noted that the CO section shown in FIG. 4 has a vacantspace which is not present in the CO section shown in FIG. 5. However,this vacant space exists in the arbitrary cell length direction. As isclear from FIG. 1, there are inherently many vacant spaces in thearbitrary cell length direction. Therefore, even if the size in thearbitrary cell length direction is increased as a result of theapplication of an embodiment of the present invention, the increasedsize will lead to no increase or an extremely slight, if any, increasein cost. If anything, the advantage gained by the application of thepresent invention, namely, the advantage that there is no need to expandthe standard cell length or use the upper wirings more than offsets thedisadvantage that the size in the arbitrary cell length direction islarger. Therefore, the application of the present invention is effectivein reducing cost.

Further, as a result of an embodiment of the application of the presentinvention, the wiring pattern layouts for the first wiring layer (1M)and polysilicon are simpler in shape thanks to fewer vertices and bends.The application of the present invention is advantageous from theviewpoint of design for manufacturing (DFM) in that it contributes toreduced man-hours for mask preparation including the OPC process anddesign, thus providing further reduced manufacturing cost and improvedyield.

Second Application Example

FIGS. 6A and 6B illustrate a circuit symbol and equivalent circuitdiagram of a clock buffer cell.

A clock buffer cell is a cell including an even number of stages ofcascaded inverters. This type of cell is designed so that the clockoutput from the cell has the same duty ratio to the extent possible.Therefore, a clock buffer is characterized in includinglarger-than-normal PMOS transistors or smaller-than-normal NMOStransistors.

A specific clock buffer circuit includes two cascaded inverters INV1 andINV2 shown in FIG. 6A. Each of the inverters INV1 and INV2 includes twoinverters connected in parallel as shown in FIG. 6B. Thus, when each ofthe inverters INV1 and INV2 of the clock buffer at the first and secondstages includes two inverters connected in parallel, the inverters offersufficient driving capability. In addition, the present invention ismore readily applicable to the clock buffer.

FIG. 7 illustrates an example in which the circuit shown in FIG. 6 islaid out with a double height cell.

In this layout diagram, a VDD line 31D is arranged at the center of thestandard cell length and extends in the arbitrary cell length direction.Two VSS lines 31S1 and 31S2 are arranged parallel to the VDD line 31Dand along the center of the width of one of the short sides on bothsides along the standard cell length. These three power lines are formedby using the second wiring layer (2M).

A specific description of the circuit configuration in the cell and theconnections is omitted because the circuit itself is simple. Here, theelement isolation insulating layer 10, PMOS active regions 11P and 12P,and NMOS active regions 11N and 12N are arranged in the same manner asin the first application example as like components as those in thefirst application example denoted by like reference numerals. Contactwith the active regions is achieved by providing branches of the powerlines in the first application example. Here, however, contact with theactive regions is achieved by providing power connection lines 39D1,39D2, 39S1 and 39S2 that are formed with the first wiring layer (1M).

Internal wirings 36 and 37 are formed with the first wiring layer (1M)to connect the inverters INV1 and INV2 together as shown in FIG. 6B. Onthe other hand, an internal wiring 38 is formed with the first wiringlayer (1M) to serve as an output wiring of the inverter INV2. The samewiring 38 extends under the VDD line 31D in the standard cell lengthdirection.

Common gate electrodes 25 and 26 are arranged parallel to each other andextend in the standard cell length direction as with the common gateelectrodes 21 to 23 (FIG. 4) in the first application example. It shouldbe noted that the CMOS pairs formed by these common gate lines are shownin the layout diagram of FIG. 7. These CMOS pairs are denoted by likereference numerals as those in FIG. 6B.

In this layout, PMOS transistors can be formed as far as in the regionclose to the VDD line which cannot be used in an ordinary single heightcell, as with the layout in FIG. 4. Further, it is possible to designthe layout with a simple wiring layer pattern without increasing thesize in the standard cell length direction in the wiring layers up tothe first wiring layer (1M). This makes it possible to increase the PMOSsize without increasing the cell area or vacant spaces, thus providing alow-cost semiconductor integrated circuit with high yield.

FIG. 8 is a layout diagram of a cell having a VSS line 31S that isarranged at the center of the standard cell length and extends in thearbitrary cell length direction. This layout is also possible in thefirst application example shown in FIG. 4.

The cell shown in FIG. 8 differs from that shown in FIG. 7 in that theVSS line 31S is arranged at the center, and that VDD lines 31D1 and 31D2are arranged along the short sides of the cell on both sides in thestandard cell length direction. As a result, the layout of the NMOS andPMOS transistors in the standard cell length direction is opposite tothat shown in FIG. 7. The cell shown in FIG. 8 is similar to that shownin FIG. 7 in all other respects.

Comparative Example 2

FIG. 9 is a layout diagram of a cell that serves as a comparativeexample of those shown in FIGS. 7 and 8.

In the horizontal layout shown in FIG. 9, it is impossible to bring thePMOS active regions close to the VDD line as can be done in the cellshown in FIG. 7 and bring the NMOS active regions close to the VSS lineas can be done in the cell shown in FIG. 8. The cell shown in FIG. 9 isdisadvantageous in that the transistors are limited by the above twoaspects and cannot be increased in size. Further, each of the commongate electrodes 25 and 26 is H-shaped. As a result, the same electrodes25 and 26 are disadvantageous in that they require a larger layout areain the arbitrary cell length direction than the same electrodes 25 and26 in linear shape shown in FIGS. 7 and 8. Moreover, an internal wiringdenoted by reference numeral 36+37 that serves the purpose of theinternal wirings 36 and 37 shown in FIGS. 7 and 8 and the internalwiring 38 are complex in shape. Because of these reasons, this cell hasa larger size in the arbitrary cell length direction. Moreover, it isdifficult to perform the OPC process when the cell is miniaturized. As aresult, it is highly likely that the yield will decline.

In other words, the cell layouts shown in FIGS. 7 and 8 to which thepresent invention is applied resolve the disadvantages of the celllayout shown in FIG. 9.

Third Application Example

FIG. 10 illustrates an equivalent circuit diagram of a third applicationexample according to the modification of the second application example.

As compared to the clock buffer shown in FIG. 6B, that shown in FIG. 10has a large PMOS transistor P10a rather than the two PMOS transistorsP11 and P12 provided in the inverter INV1 shown in FIG. 6B. The sameholds true for the inverter INV2. That is, the clock buffer shown inFIG. 10 has a large PMOS transistor P10b rather than the two PMOStransistors P13 and P14 shown in FIG. 6B.

FIG. 11 illustrates a plan view of a cell that achieves the circuitshown in FIG. 10.

The comparison of the cells shown in FIGS. 7 and 11 reveals that the twoseparate PMOS active regions 12P and 11P in FIG. 7 are replaced by asingle vertically long PMOS active region 13P in FIG. 11. Thiseliminates the need for an isolation region (part of the elementisolation insulating layer 10) between the active regions required inFIG. 7, thus making it possible to increase the sizes of the PMOStransistors. Alternatively, if the PMOS transistors are maintained inthe same size, it is possible to increase the sizes of the NMOStransistors.

It should be noted that the cell shown in FIG. 11 can be modified in thesame manner as the cell shown in FIG. 7 is modified to provide the cellshown in FIG. 8.

Fourth Application Example

FIGS. 12A and 12B illustrate a circuit symbol and equivalent circuitdiagram of a clock buffer cell capable of dividing the output into aplurality of branches as another modification example of the clockbuffer cell shown in FIGS. 6A and 6B.

The circuit shown in FIGS. 12A and 12B differs from that shown in FIGS.6A and 6B in that the inverter INV2 at the subsequent stage is dividedinto inverters INV2A and INV2B, each of which has an output node. InFIG. 12B, an internal wiring 38A making up the output node of theinverter INV2A and an internal wiring 38B making up the output node ofthe inverter INV2B are provided separately from each other. The circuitshown in FIGS. 12A and 12B is similar to that shown in FIGS. 6A and 6Bin all other respects.

FIG. 13 illustrates an example in which the circuit shown in FIG. 12 islaid out with a double height cell.

In the clock buffer with branched outputs, the output node is separatedinto the internal wirings 38A and 38B. As a result, there is no need forthe internal wiring of the output node to intersect the VDD line 31D atthe center. This makes it possible to form the VDD line 31D (and VSSlines 31S1 and 31S2) with the first wiring layer (1M) as illustrated inFIG. 13. The connections between the power lines and active regions areachieved by the branch power lines extending from the main power lines.The circuit shown in FIG. 13 is similar to that shown in FIG. 7 in allother respects.

2. Second Embodiment

The second embodiment is a modification of the circuits shown in FIGS. 7and 8 using a triple height cell that has a standard cell length that isthree times the basic cell length.

FIG. 14 illustrates a layout diagram according to the second embodiment.

If, for example, the double height portion of the upper two stages inFIG. 14 is considered to be the same as the cell shown in FIG. 8, thelowermost stage portion is added to the cell shown in FIG. 8.Alternatively, if the double height portion of the lower two stages inFIG. 14 is considered to be the same as the cell shown in FIG. 7, theuppermost stage portion is added to the cell shown in FIG. 7. In FIG.14, the additional portions are denoted by new reference numerals fromthe former viewpoint.

It should be noted that the equivalent circuit achieved by the layoutdiagram shown in FIG. 14 includes three parallel inverters in place ofeach of the inverters INV1 and INV2 shown in FIG. 6B.

In the additional portion, reference numeral 10P denotes a PMOS activeregion, and reference numeral 10N an NMOS active region. Further, a VSSline denoted by reference numeral 31D0 is added. The VDD lines 31D0 and31D1 are provided respectively with the power connection lines 39S2 and39D2 that are formed with the first wiring layer (1M). The same lines39S2 and 39D2 are branch lines adapted to connect the NMOS active region10N and PMOS active region 10P respectively to the power lines.

It should be noted that the internal wiring 36+37 is disposed to extendas long as the length of three basic cells. However, the internalwirings 36 and 37 can be similarly connected together to extend as longas the length of two standard cells in FIGS. 7 and 8. Therefore, this isnot a special characteristic of a triple height cell.

Other components of the cell shown in FIG. 14 can be basically explainedby analogy of the double height cells shown in FIGS. 7 and 8.

It should be noted that the corrections made by changing a double heightcell to a triple height cell can be applied to multi-height cells equalto or greater than triple height cell using the same technique.

Still further, the advantages of a double height cell are similarlyinherited by multi-height cells equal to or greater than triple heightcell.

3. Third Embodiment

Multi-height cells equal to or greater than triple height cell can beused to produce a non-rectangular cell that is bent in the shape of L asa whole.

In a layout example according to the standard cell system as shown inFIG. 1, in general, there are likely many gaps in the arbitrary celllength direction. However, there is often not much leeway in space inthe standard cell length direction. Therefore, if one wishes to increasethe number of CMOS pairs as a whole while restricting the height in thestandard cell length direction, this goal can be achieved byaccommodating some of the CMOS pairs in the L-shaped bent portion in thearbitrary cell length direction. This solution often produces no wastedlayout area.

The third embodiment is designed to meet such a need. The layout asshown in FIG. 15 can be, for example, used.

In FIG. 15, a cell having three CMOS pairs as that shown in FIG. 14 isachieved by combining the layout of the double height cell shown in FIG.7 and the layout the CMOS pairs on the right side of the single heightcell shown in FIG. 9. It should be noted, however, that the two metalwiring layers shown in FIG. 9 are used. On the other hand, a common gateline denoted by reference numeral 27 has a shape in plan view that isdivided into branches under the VDD line 31D for three CMOS pairs. TheseCMOS pairs make up three parallel inverters in the first stage. Threeparallel inverters in the subsequent stage include three CMOS pairsformed by connecting a common gate electrode 28 and the H-shaped commongate electrode 26 (refer to FIG. 9) together with the internal wiring36+37 that is formed with the first wiring layer (1M). In addition tothe above, a power branch line connected to the NMOS active region 12Nis denoted by reference numeral 39S0, and a power branch line connectedto the PMOS active region 12P by reference numeral 39D0. All othercomponents were already described with reference to FIGS. 7 and 9, andtherefore the description thereof is omitted.

In the present embodiment, the functions of a triple height cell can beachieved with the standard cell height of a double height cell. Thisallows a greater degree of freedom in the layout, making it possible tochoose between the layouts shown in FIGS. 14 and 15 according to theconditions surrounding the layout location when many triple height cellsare laid out. This is significantly advantageous in that more efficientlayout is possible. It should be noted, however, that the common gateline 27 is divided into branches where it intersects the VDD line 31D inFIG. 15. Therefore, the PMOS active regions 12P and 11P cannot bebrought very close to the VDD line 31D. However, the layout shown inFIG. 15 has advantages that more than offset the above disadvantage,which makes this layout effective.

It should be noted that, including this third embodiment, the number ofcomplementary transistor pairs to be driven in phase or N need notnecessarily agree with the number of complementary transistor pairs or Mthat is appropriate to the standard cell length of multi-height layout.That is, a multi-height layout is possible that satisfies therelationship N≥M≥2.

4. Modification Examples

Modification examples of substrate contacts will be shown next.

In the first to third embodiments, substrate contacts are not shown inthe layout diagrams.

FIGS. 16 and 17 illustrate two examples of how to arrange substratecontacts. These figures illustrate in detail the substrate contactportions of the cell shown in FIG. 4. The same substrate contact layouttechnique is similarly applicable to the other layout diagrams.

Basically, in order to dispose gate polysilicon layer wirings (commongate lines) in the presence of substrate contacts SCH, the same contactsSCH and doped regions are removed, as appropriate only where the gatepolysilicon layers are disposed. Here, the substrate contacts SCH arealso referred to as taps. More specifically, an N-type doped region 14Nthat is higher in concentration is formed on the surface of the tapregion where the PMOS active regions 12P and 11P and the elementisolation insulating layer 10 are connected together in the deep side ofthe substrate. The substrate contacts SCH serve as connection plugsbetween the N-type doped region 14N and first wiring layer (1M). Thisallows for the channel forming regions of the PMOS transistors formed inthe PMOS active regions 11P and 12P to be supplied with VDD voltage fromthe VDD line 30D. Further, the source region of the PMOS transistors issupplied with power by the branch from the VDD line 30D and the contactsconnected to the branch.

On the other hand, many substrate contacts SCH are provided in the VSSlines 30S1 and 30S2 for the same purpose as above. The substratecontacts SCH in these areas are provided to connect the NMOS activeregion 11N or 12N to the VSS voltage. Strictly speaking, the channelforming region formed in the NMOS active region 11N or 12N or thesubstrate is connected to the VSS voltage. That is, a P-type dopedregion 14P that is higher in concentration is formed on the surface ofthe tap region where the NMOS active region 12N or 11N and the elementisolation insulating layer 10 are connected together in the deep side ofthe substrate. The substrate contacts SCH serve as connection plugsbetween the P-type doped region 14P and first wiring layer (1M). Thisallows for the channel forming regions of the NMOS transistors formed inthe NMOS active regions 11N and 12N to be supplied with VSS voltage.Further, the source region of the NMOS transistors is supplied withpower by the branch from the VSS line 30S1 or 30S2 and the contactsconnected to the branch.

Alternatively, a tapless circuit cell having none of the substratecontacts SCH (referred to as the taps) as shown in FIG. 17 may be used.In order to provide the substrate contacts SCH not provided by thetapless circuit cell, a tap cell 2 is also used.

The tap cell 2 is laid out as appropriate in the gap formed asappropriate in the arbitrary cell direction shown in FIG. 1. Therefore,careful consideration is given to ensure that the layout of the circuitcell is not affected by the tap cell 2.

The first to third embodiments described above provide the followingadvantages.

Firstly, the number of horizontal (arbitrary cell length direction)metal wirings can be reduced, thus allowing for effective use of themetal wiring resources.

Secondly, increased wiring resources eliminate the need to use metal inthe upper layers.

Thirdly, polysilicon gate wirings (common gate lines) are disposed wherethey would not exist if the present invention was not applied, thuseliminating the horizontal polysilicon gate wirings and providingincreased wiring resources.

Fourthly, the polysilicon gate wirings are simpler in shape.

Fifthly, thanks to the polysilicon gate wirings that are simpler inshape, there is more layout area in the diffusion regions (activeregions) or the layout is easier to do.

Sixthly, since the metal and polysilicon wirings and diffusion regionsare easier to lay out, the geometries are no longer complex, which iseffective from the viewpoint of design for manufacturing (DFM).

Seventhly, where a VDD line is shared in a multi-height cell, the PMOSsize can be increased, thus providing improved transistor mounting areaefficiency.

Similarly, where a VSS line is shared in a multi-height cell, the NMOSsize can be increased, thus providing improved transistor mounting areaefficiency also in this respect.

The above advantages are achieved by elaborately taking advantage of thefact that, in a CMOS circuit, a signal is commonly connected to the gateterminals of the paired PMOS and NMOS transistors, In the case of aninverter, for example, a signal is connected to the gate terminals ofthe CMOS pair. In the first to third embodiments, when the cell inputsignals and the intracell signals are connected to the gate terminals ofa plurality of CMOS pairs, a multi-height cell is intentionally used tolay out these CMOS pairs vertically.

The present application contains subject matter related to thatdisclosed in Japanese Priority Patent Application JP 2009-198547 filedin the Japan Patent Office on Aug. 28, 2009, the entire content of whichis hereby incorporated by reference.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factor in so far as they arewithin the scope of the appended claims or the equivalents thereof.

What is claimed is:
 1. A semiconductor integrated circuit, wherein adesired circuit is formed by combining and laying out plurality ofstandard cells and connecting the cells together, of which the celllength, i.e., the gap between a pair of opposed sides, is standardized,the plurality of standard cells forming the desired circuit includecomplementary in-phase driven standard cells, each of which includes aplurality of complementary transistor pairs that are complementary inconductivity type to each other and have their gate electrodes connectedtogether, and N (≥2) pairs of all the complementary transistor pairs aredriven in phase, and the size of the standardized cell length of thecomplementary in-phase driven standard cell is defined as an M-fold celllength which is M (N≥M≥2) times the basic cell length which isappropriate to the single complementary transistor pair, and the commongate electrodes of at least M pairs of the N complementary transistorpairs to be driven in phase are arranged linearly in the direction ofthe M-fold cell length.
 2. The semiconductor integrated circuit of claim1, wherein single height cells or standard cells having the basic celllength and multi-height cells or the complementary in-phase drivenstandard cells having the M-fold cell length are arranged adjacent toeach other to share power lines so as to form the desired circuit. 3.The semiconductor integrated circuit of claim 2, wherein themulti-height cell has a total of (M+1) power lines which is the sum of(M−1) power wirings that are arranged parallel to each other to extendin an arbitrary cell length direction orthogonal to the M-fold celllength with a separation pitch equal to the basic cell length obtainedby dividing the M-fold cell length into M equal parts and two sharedpower wirings, each of which is shared with an adjacent cell at thecenter of the width of one of two cell boundaries, one on each sidealong the M-fold cell length, the (M+1) power lines include sourcevoltage lines and reference voltage lines that are alternately arranged,and the single height cell connected to a pair of the source voltageline and reference voltage line arranged adjacent and parallel to eachother is arranged adjacent to the multi-height cell in the arbitrarycell length direction.
 4. The semiconductor integrated circuit of claim3, wherein two active regions of the same conductivity type wheretransistors are respectively formed are arranged line-symmetrically withrespect to the center line of the width of each of the (M−1) powerwirings, and the common gate electrodes are arranged linearly tointersect each of one of the active regions, power wirings and the otherof the active regions.
 5. The semiconductor integrated circuit of claim4, wherein all the gate electrodes overlapping an element isolationregion provided between the two active regions are the common gateelectrodes extending from one of the two active regions to the other ofthe two active regions and intersecting the element isolation region. 6.The semiconductor integrated circuit of claim 3, wherein the (M+1) powerlines and all intracell connection lines are formed with a first metalwiring layer, and intercell signal lines are formed with a second metalwiring layer.
 7. The semiconductor integrated circuit of claim 2,wherein the multi-height cell is a non-rectangular cell that surroundsthe single height cell in an L-shaped manner by including first andsecond rectangular sections, the first rectangular section having theM-fold cell length in which M complementary transistor pairs of all thecomplementary transistor pairs to be driven in phase are arranged, andthe second rectangular section extending along one of two sides that areopposed to each other in the direction of the standardized cell lengthof the first rectangular section.
 8. The semiconductor integratedcircuit of claim 1, wherein a plurality of standard cells forming thedesired circuit include at least one non-rectangular standard cell thatis L-shaped as a whole in plan view by comprising first and secondrectangular sections, the first rectangular section having the M-foldcell length in which M complementary transistor pairs of all thecomplementary transistor pairs to be driven in phase are arranged, andthe second rectangular section extending along one of two sides that areopposed to each other in the direction of the standardized cell lengthof the first rectangular section.
 9. A semiconductor integrated circuitcomprising: first voltage lines that extend in a first direction, thefirst direction differs from a second direction; second voltage linesthat extend in the first direction, one of the second voltage lines isbetween one of the first voltage lines and a different one of the firstvoltage lines; a first active region of a first conductivity type, thefirst conductivity type differs from a second conductivity type; asecond active region of the second conductivity type, the first activeregion and the second active region are between the one of the firstvoltage lines and the one of the second voltage lines: a third activeregion of the first conductivity type that an element isolation regionisolates from the first active region and the second active region; afourth active region of the second conductivity type that the elementisolation region isolates from the second active region and the thirdactive region, the third active region and the fourth active region arebetween the one of the second voltage lines and the different one of thefirst voltage lines; a first gate electrode configured to drive aplurality of complementary transistor pairs, the first gate electrodeextends along the second direction to overlap at least the first activeregion and the second active region and the third active region and thefourth active region; and a second gate electrode configured to drive aplurality of complementary transistor pairs, the second gate electrodeextends along the second direction to overlap at least the first activeregion and the second active region and the third active region and thefourth active region.
 10. A semiconductor integrated circuit as setforth in claim 9, further comprising: a fifth active region of the firstconductivity type that the element isolation region isolates from thefirst active region and the second active region and the third activeregion and the fourth active region, the first gate electrode and thesecond gate electrode extend along the second direction to overlap thefifth active region.
 11. A semiconductor integrated circuit as set forthin claim 9, wherein the third active region continuously extends in thefirst direction.
 12. A semiconductor integrated circuit as set forth inclaim 9, wherein the first gate electrode has a straight linear shape.13. A semiconductor integrated circuit as set forth in claim 9, whereinthe first gate electrode intersects with the one of the second voltagelines.
 14. A semiconductor integrated circuit as set forth in claim 9,wherein the first gate electrode is configured to drive at least part ofa first logic circuit and at least part of a second logic circuit, afunction the second logic circuit differs from a function of the firstlogic circuit.
 15. A semiconductor integrated circuit as set forth inclaim 14, wherein the first logic circuit is NAND circuit, and thesecond circuit is an inverter circuit.
 16. A semiconductor integratedcircuit as set forth in claim 9, wherein the first gate electrode isconfigured to drive a plurality of complementary transistor pairs, thesecond gate electrode is configured to drive another plurality of thecomplementary transistor pairs.
 17. A semiconductor integrated circuitas set forth in claim 9, wherein the second gate electrode has astraight linear shape.
 18. A semiconductor integrated circuit as setforth in claim 9, wherein the second gate electrode intersects with theone of the second voltage lines.
 19. A semiconductor integrated circuitas set forth in claim 9, wherein the first gate electrode and the secondgate electrode are formed from the electrically conductive material. 20.A semiconductor integrated circuit as set forth in claim 9, wherein alength of the first gate electrode is same as a length of the secondgate electrode.
 21. A semiconductor integrated circuit as set forth inclaim 9, wherein the second gate electrode is adjacent to the first gateelectrode.
 22. A semiconductor integrated circuit as set forth in claim9, wherein the first gate electrode is configured to drive a pluralityof inverters, the second gate electrode is configured to drive anotherplurality of the inverters.
 23. A semiconductor integrated circuit asset forth in claim 10, further comprising: a sixth active region of thesecond conductivity type that the element isolation region isolates fromthe first active region and the second active region and the thirdactive region and the fourth active region and the fifth active region.24. A semiconductor integrated circuit as set forth in claim 23, whereinthe fifth active region and the sixth active region are between the oneof the first voltage lines and a different one of the second voltagelines, the first gate electrode extends along the second direction whileoverlapping at least the fifth active region and the sixth activeregion.
 25. A semiconductor integrated circuit as set forth in claim 24,wherein one of the first voltage lines is between the one of the secondvoltage lines and the different one of the second voltage lines.
 26. Asemiconductor integrated circuit as set forth in claim 9, wherein thefirst gate electrode and the second gate electrode extend in amulti-height standard cell, a cell length of the multi-height standardcell is an integral multiple of a cell length of a single heightstandard cell.
 27. A semiconductor integrated circuit as set forth inclaim 26, further comprising: a transistor in the multi-height standardcell, wiring is connected to a source region of the transistor or adrain region of the transistor.
 28. A semiconductor integrated circuitas set forth in claim 27, wherein a first layer includes the wiring. 29.A semiconductor integrated circuit as set forth in claim 28, wherein thewiring crosses the one of the second voltage lines at an intersectionpoint, the one of the second voltage lines is physically isolated fromthe wiring at the intersection point.
 30. A semiconductor integratedcircuit as set forth in claim 28, wherein a second layer includes thefirst voltage lines and the second voltage lines.
 31. A semiconductorintegrated circuit as set forth in claim 30, wherein a gate layer, thefirst layer and the second layer are arranged in order.
 32. Asemiconductor integrated circuit as set forth in claim 30, wherein agate layer is under the first layer, the gate layer is under the secondlayer.